- It seperate all I/O address from the memory address(that is address space is seperate for I/O & Memory).
- CPU has distinct I/O instructions so complexity in instructions set increases.
- If the addresses of the interfacing registors(I/O) is placed on the address lines, the I/O Read & I/O Write control lines are enable.If the memory address is placed on the address line, the Memory Read & Memory Write control lines are enable.
- This technique can be used only with microprocessor that have seperate IN & OUT instructions & special I/O Write & Read control outputs.
MEMORY MAPPED I/O
- This technique can be used with any microprocessor.
- Same address space is used for both Memory & I/O.
- It allows the microprocessor to send the same instructions for both I/O transfer & Memory transfer.
- Some of CPUs addressable space is reservedfor Memory or same for I/O.
- If total address location = 0 –>K
M = no of address for I/O
N = no of address for M
then K = M + N
- Only one set of Read/Write control signals are there.
- In this technique, CPU must regularly check/poll each channel or post in turn.
- It is time consuming as CPU has pause & poll every port.
- Post status is examined in case action is required by computer for example: CPU is programmed to read the keyboard, it is periodically checks if a character has been entered.
- Usually used for small systems.
The idea of following is to repeatedly input &/ or output by the using a polling loop in the program.
- It is wasteful of CPU time as it involves CPU through out the I/O process.
- In interrupt I/O, processor after sending command to I/O module(for execution of any instruction) is free to perform any other task. When I/O module checks the states of device and if it is ready then I/O module will it self interrupt the microprocessor to request service. On receiving interrupt request, CPU finished is the instruction it is executing, save the contents of IP & Flag register & then executes the interrupt service routine.
- More complex Hardware & Software.
- It makes for efficient use of CPUs time & capacities.