PURPOSE & GMPLEMENTATION OF 8088/86 WAIT,HALT & HOLD STATE

HALT

   The instruction is used at the end of a program to stop the microprocessor from progressing through more ” instructions”. In program memory.

    Only a rest or  interrupt input to the MPU is in the generic MPU when the MPU is in the halt mode.

HOLD

  In hold state, MPU gives control of its buses to another device (external) like DMA and puts some of its pin on high-impedance state.

  A HOLD input notifies the MPU that another device wants to use the address & data buses. This may occur during DMA operations. Upon receiving a HOLD input, the CPU will complete current data transfers on the buses. Then its address, data, RDn, WRn & IO/Mn pins are three-stated so as not to interface with data transfers on the buses. A HOLD output indicates to a peripheral that a hold request has been received & microprocessor will relinguish control of the buses in the next clock cycle.

WAIT

   The peripherals or memories are too slow as compared to the procassing speed of the microprocessor. The microprocessor goes into the WAIT state if & unless the device is not ready to read/write.

  If READY (from the peripheral device) is low, the MPU interprets this as a request to enter the wait state.

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